NXP Semiconductors /MIMXRT1021 /USBPHY /CTRL_CLR

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Interpret as CTRL_CLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENOTG_ID_CHG_IRQ)ENOTG_ID_CHG_IRQ 0 (ENHOSTDISCONDETECT)ENHOSTDISCONDETECT 0 (ENIRQHOSTDISCON)ENIRQHOSTDISCON 0 (HOSTDISCONDETECT_IRQ)HOSTDISCONDETECT_IRQ 0 (ENDEVPLUGINDETECT)ENDEVPLUGINDETECT 0 (DEVPLUGIN_POLARITY)DEVPLUGIN_POLARITY 0 (OTG_ID_CHG_IRQ)OTG_ID_CHG_IRQ 0 (ENOTGIDDETECT)ENOTGIDDETECT 0 (RESUMEIRQSTICKY)RESUMEIRQSTICKY 0 (ENIRQRESUMEDETECT)ENIRQRESUMEDETECT 0 (RESUME_IRQ)RESUME_IRQ 0 (ENIRQDEVPLUGIN)ENIRQDEVPLUGIN 0 (DEVPLUGIN_IRQ)DEVPLUGIN_IRQ 0 (DATA_ON_LRADC)DATA_ON_LRADC 0 (ENUTMILEVEL2)ENUTMILEVEL2 0 (ENUTMILEVEL3)ENUTMILEVEL3 0 (ENIRQWAKEUP)ENIRQWAKEUP 0 (WAKEUP_IRQ)WAKEUP_IRQ 0 (ENAUTO_PWRON_PLL)ENAUTO_PWRON_PLL 0 (ENAUTOCLR_CLKGATE)ENAUTOCLR_CLKGATE 0 (ENAUTOCLR_PHY_PWD)ENAUTOCLR_PHY_PWD 0 (ENDPDMCHG_WKUP)ENDPDMCHG_WKUP 0 (ENIDCHG_WKUP)ENIDCHG_WKUP 0 (ENVBUSCHG_WKUP)ENVBUSCHG_WKUP 0 (FSDLL_RST_EN)FSDLL_RST_EN 0RSVD1 0 (OTG_ID_VALUE)OTG_ID_VALUE 0 (HOST_FORCE_LS_SE0)HOST_FORCE_LS_SE0 0 (UTMI_SUSPENDM)UTMI_SUSPENDM 0 (CLKGATE)CLKGATE 0 (SFTRST)SFTRST

Description

USB PHY General Control Register

Fields

ENOTG_ID_CHG_IRQ

Enable OTG_ID_CHG_IRQ.

ENHOSTDISCONDETECT

For host mode, enables high-speed disconnect detector

ENIRQHOSTDISCON

Enables interrupt for detection of disconnection to Device when in high-speed host mode

HOSTDISCONDETECT_IRQ

Indicates that the device has disconnected in high-speed mode

ENDEVPLUGINDETECT

For device mode, enables 200-KOhm pullups for detecting connectivity to the host.

DEVPLUGIN_POLARITY

For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in

OTG_ID_CHG_IRQ

OTG ID change interrupt. Indicates the value of ID pin changed.

ENOTGIDDETECT

Enables circuit to detect resistance of MiniAB ID pin.

RESUMEIRQSTICKY

Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it

ENIRQRESUMEDETECT

Enables interrupt for detection of a non-J state on the USB line

RESUME_IRQ

Indicates that the host is sending a wake-up after suspend

ENIRQDEVPLUGIN

Enables interrupt for the detection of connectivity to the USB line.

DEVPLUGIN_IRQ

Indicates that the device is connected

DATA_ON_LRADC

Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.

ENUTMILEVEL2

Enables UTMI+ Level2. This should be enabled if needs to support LS device

ENUTMILEVEL3

Enables UTMI+ Level3

ENIRQWAKEUP

Enables interrupt for the wakeup events.

WAKEUP_IRQ

Indicates that there is a wakeup event

ENAUTO_PWRON_PLL

Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended

ENAUTOCLR_CLKGATE

Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended

ENAUTOCLR_PHY_PWD

Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended

ENDPDMCHG_WKUP

Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended

ENIDCHG_WKUP

Enables the feature to wakeup USB if ID is toggled when USB is suspended.

ENVBUSCHG_WKUP

Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.

FSDLL_RST_EN

Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.

RSVD1

Reserved.

OTG_ID_VALUE

Almost same as OTGID_STATUS in USBPHYx_STATUS Register

HOST_FORCE_LS_SE0

Forces the next FS packet that is transmitted to have a EOP with LS timing

UTMI_SUSPENDM

Used by the PHY to indicate a powered-down state

CLKGATE

Gate UTMI Clocks

SFTRST

Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers

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